The present invention relates generally to deep trench capacitors fabricated in a semiconductor substrate, and, more particularly, to a modified wet bottling process for small diameter deep trench capacitors.
Deep trench capacitors are used in a variety of semiconductor chips for high areal capacitance and low device leakage. Typically, a deep trench capacitor provides a capacitance in the range from about 4 fF (femto-Farad) to about 120 fF. A deep trench capacitor may be employed as a charge storage unit in a dynamic random access memory (DRAM), which may be provided as a stand-alone semiconductor chip, or may be embedded in a system-on-chip (SoC) semiconductor chip. A deep trench capacitor may also be employed in a variety of circuit applications such as a charge pump or a capacitive analog component in a radio-frequency (RF) circuit.
Semiconductor-on-insulator (SOI) devices formed on an SOI substrate or on a hybrid substrate provide high performance in advanced semiconductor chips. In SOI devices, the capacitive coupling between a substrate and semiconductor devices is reduced by the presence of a buried insulator layer. By forming a deep trench capacitor in the SOI substrate, SOI logic devices such as SOI transistors and deep trench capacitors may be formed on the same SOI substrate, thereby enabling embedding of deep trench capacitors into the SOI substrate that also contain high performance SOI logic devices. Such embedded deep trench capacitors enable various functionality including embedded dynamic access memory (eDRAM) and other embedded electronic components requiring a capacitor.
Capacitance of a deep trench capacitor employed in the SOI substrate may be increased by forming a bottle shaped trench, which has a greater width at a bottom portion beneath a buried insulator layer than at an upper portion located at and above the buried insulator layer. Such a bottle shaped trench benefits from an increased surface area due to the shape of the trench, for example, the bottle shape, since the area of a node dielectric increases almost linearly with the width of the bottom portion of the deep trench, while consuming a minimal area in the upper portion so that use of the area of the top semiconductor layer by the deep trench capacitor is minimized.
For the manufacture of such a bottle shaped trench, however, it is necessary to protect adjoining portions of the top semiconductor layer around the upper portion of the deep trench during the expansion of the bottom portion of the deep trench to form a bottle shaped cavity and during the formation of the buried plate. In general, formation of a deep trench may be divided into two processing steps, between which a top semiconductor collar dielectric is formed on exposed sidewall surfaces of the top semiconductor layer. In one example, the collar dielectric may be typically formed by converting a sidewall of the top semiconductor layer, thus reducing the material of the top semiconductor layer that is available for formation of semiconductor devices. In another example, the collar dielectric may be typically formed by depositing a non-conformal dielectric layer within the deep trench and subsequently removing it from the lower portion. In another example, the collar dielectric may be typically formed by depositing a sacrificial material to fill a lower portion of the deep trench, followed by depositing a non-conformal dielectric layer within a remaining opening in the upper portion of the deep trench, subsequently removing a bottom portion of the collar dielectric and then removing the sacrificial material from the lower portion. In sum, protection of portions of the top semiconductor layer adjoining the deep trench requires multiple additional processing steps, thereby increasing processing complexity and cost.